A Cache Energy Optimization Technique for STT-RAM Last Level Cache

摘要

Last level caches (LLCs) occupy a large chip-area and there size is expectedto grow further to offset the limitations of memory bandwidth and speed. Due tohigh leakage consumption of SRAM device, caches designed with SRAM consumelarge amount of energy. To address this, use of emerging technologies such asspin torque transfer RAM (STT-RAM) has been investigated which have lowerleakage power dissipation. However, the high write latency and power of it maylead to large energy consumption which present challenges in its use. In thisreport, we propose a cache reconfiguration based technique for improving theenergy efficiency of STT-RAM based LLCs. Our technique dynamically adjusts theactive cache size to reduce the cache leakage energy consumption with minimumperformance loss. We choose a suitable value of STT-RAM retention time foravoiding refresh overhead and gaining performance. Single-core simulations havebeen performed using SPEC2006 benchmarks and Sniper x86-64 simulator. Theresults show that while, compared to an STT-RAM LLC of similar area, an SRAMLLC incurs nearly 100% loss in energy and 7.3% loss in performance; ourtechnique using STT-RAM cache saves 21.8% energy and incurs only 1.7% loss inperformance.